`timescale 1ns / 1ns

module cycle_left (
    input  [5:0] in,
    output [5:0] out
);
    assign out[5:1] = in[4:0];
    assign out[0]   = in[5];
endmodule

module sequence_generator (
    input clk,
    input rst_n,
    output reg data
);
    reg  [5:0] seq;
    wire [5:0] seq_out;
    initial begin
        seq = 6'b001011;
    end

    cycle_left cl (
        .in (seq),
        .out(seq_out)
    );

    always @(posedge clk) begin
        if (rst_n == 0) begin
            data <= 0;
        end else begin
            data <= seq[5];
            seq  <= seq_out;
        end
    end
endmodule
